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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
Figure 50: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK#
CK
WL = 1
CA[9:0]
Bank n
col addr
Col addr
Bank n
Bank n
row addr
Row addr
t WR
t RP
CMD
WRITE
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVATE
NOP
Case 1: t DQSSmax
DQS#
DQS
t DQSSmax
Completion of burst WRITE
DQ
D IN A0
D IN A1
D IN A2
D IN A3
Case 2: t DQSSmin
DQS#
DQS
t DQSSmin
DQ
D IN A0
D IN A1
D IN A2
D IN A3
Transitioning data
Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge function. When a READ
or WRITE command is issued to the device, the auto precharge bit (AP) can be set to
enable the active bank to automatically begin precharge at the earliest possible mo-
ment during the burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, then normal READ or
WRITE burst operation is executed and the bank remains active at the completion of
the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge func-
tion is engaged. This feature enables the PRECHARGE operation to be partially or com-
pletely hidden during burst READ cycles (dependent upon READ or WRITE latency),
thus improving system performance for random data access.
READ Burst with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge
function is engaged.
These devices start an auto precharge on the rising edge of the clock BL/2 or BL/2 - 2 +
RU( t RTP/ t CK) clock cycles later than the READ with auto precharge command, which-
ever is greater. For auto precharge calculations see Table 43 (page 73).
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
71
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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